In a processor, such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor), which is used in a computer, it is possible to enhance processing performance thereof by increasing its clock frequency. In recent years, however, the enhancement of the performance of the processor by increasing the clock frequency is reaching the limit. Under the circumstances, the processor tends to be multi-cored for further enhancement of the processing performance.
If the processor is multi-cored, a plurality of processor cores (hereinafter simply referred to as “the cores”) are mounted as processing sections on an LSI (Large Scale Integrated circuit) chip. In the multi-cored processor, to ensure the throughput of processing, the processor is devised such that a cache memory or a main storage device is divided into a plurality of banks to access from the cores to the cache memory or the main storage device on a bank basis.
[Patent Document 1] National Publication of translated version of PCT Application No. 2006-522385
By the way, when an access is made to the cache memory divided into the banks from each core of the processor, the access is controlled by a cache memory control circuit. If the processor is provided with only one cache memory control circuit, if requests for data acquisition are simultaneously issued from the cores, the cache memory control circuit has to sequentially process the requests. Then, in some of the cores, waiting time before reading data from the cache memory becomes longer, which results in the degraded data access performance.
Therefore, to enhance the data access performance, it is envisaged to divide the cache memory into a plurality of banks and provide a plurality of cache memory control circuits in association with the respective banks, to thereby control access to the cache memory on a bank basis. By performing the access to the cache memory on a bank basis, even when requests for data acquisition are simultaneously issued from the cores, if the destinations of the requests are different banks, the cache memory control circuits can individually perform parallel processing on the respective requests at the same time. As a result, it is possible to improve the efficiency of data acquisition.
However, the parallelization of access from the cores to the cache memory causes an increase in the chip size of the LSI having the processor mounted thereon. More specifically, to enable parallel access to the cache memory, it is necessary to arrange a plurality of data buses from the cache memory to the cores, and further, in sockets for the cores, provide wiring for the data buses, and registers and selectors for receiving the wiring. This increases the chip size of the LSI having the processor mounted thereon. The increase in the chip size causes a decrease in the number of chips cut out from a piece of a silicon wafer, and an increase in the manufacturing costs of the processor.
Moreover, the number of cores which serve as processing sections within one chip tends to be increased. Therefore, an increase in the occupied area of each core is considered to have more serious influence on the increase in the chip size hereafter.